1. Field of the Invention
The present invention relates to an error correction system of digital data for use in a digital data processing system such as a digital VTR and a digital TV, etc.. More particularly, the present invention is directed to an error correction system improving the display of a reproducing image, in a manner which the synchronizing detection errors due to the instability of synchronizing signals are minimized, when the data reproduction from a tape is performed using an ID (Identifying) error flag, and error data reproduced with a variable speed mode, for example a shuttle mode and a de-shuttle mode, is substituted for the previous field data free from errors.
2. Description of the Prior Art
A conventional digital video tape recorder (VTR) makes a synchronizing detection error due to the instability of a synchronizing signal during reproducing data from a tape. It causes all reproducing data to be wrong in the timing, thereby resulting in processing data different from data recorded in the middle of processing data after the synchronizing detection. At the reproduction of a shuttle mode or a de-shuttle mode, only parts of a tape are restored without errors, or all data recorded happens to make many errors because of the staggering of a reproducing order differing from an original status.
Typically, U.S. Pat. No. 4,799,113 describes an apparatus for processing digital data as reproduced by a digital tape recorder includes a first memory in which words or blocks of reproduced digital data written in accordance with respective write address and from which the words of written data are read out in response to read addresses selected for de-shuffling or de-interleaving of the reproduced data and a second memory storing, at addresses corresponding to the write addresses at which the words of digital data are written in the first memory, data, such as error flags, indicating the state of such words of digital data. It also occurs much loss of reproducing data from the first memory during operating of the concealment or the interpolation due to the instability of a synchronizing signal.
The object of the present invention is to improve a reproducing picture or image, making use of an ID and an error flag to generate write addresses so as to store them in a reshuffling memory while applying the same addresses to a flag memory so as to store them therein.
Another object of the present invention is to provide an error correction system of digital data for substituting an error field for a field not having errors.
Still another object of the present invention is to provide an error correction system of digital data for minimizing synchronizing detection errors as well as for preventing the staggering of the timing between data and control signals.
Yet another object of the present invention is to provide an error correction system of digital data for requiring a small number of the data and error flag storing memories without an additional circuit.